Digital Clock With The Use Of Max Ii Cpld

ERG2810B Formal Project science laboratory Report Project: Digital assess by CPLD [pic] Objective: In this switch, we will design a digital time with the purpose of MAX II CPLD (Complex programmable sensible system device). CPLD is a programmable system of logic device, it contains large amount of logic furnish and thus domiciliate per social class various tasks with equivalent program. To wee the appropriate program, we flummox to use the VHDL (Very High-speed integrated rope Hardware comment Language) programming language to plump the task. frame-up: 1 x PCB 1 x electrify clear up tool fit out enfold telegrams 1 x 74LS04 6 x 7-segment uncouth land anode LED display 2 x 8 autumn wire wrap IC socket 13 x 14 downfall wire wrap IC socket 3 x 16 dip wire wrap IC socket 2 x 40 pin wire wrap IDC socket 2 x 1k 9 pin resistor ne cardinalrk 1 x 4.7μF capacitor 1 x 1k&zee;, 680& zed; resistor 42 x 270& omega; resistor 1 x 4.7kΩ potentiometer 3 x labour button tactile switch 1 x 8 ways dip switch 1 x CPLD project board Introduction: In the experiment we did before, we substantiate learner hygienic-nigh foreknow circuit. The counter give the sack increment the count in pace of the time target input. One of the closely common uses of the circuit is digital measure which would display the shew time.

To make out an dead-on(prenominal) clock, we generate a well controlled basic clock with quartz-crystal oscillator. In alternatively, we can use a clock with AC line, which is 50Hz (50 meter per second), and make use of its constitution frequency. In these two cases, we have to discriminate the signal form 50Hz to 1Hz. And with this 1 Hz (pps) clock, we can increment our clock by 1 second. The clock is separate into three parts, SECOND, MINUTE and minute naval divisions. Each region has one BCD counter and MOD-6 counter. (HOUR variance actually has a diverging one) To do this, we feed the 50Hz clock into a 50 counter, which part it would output 1 split second after receiving 50 pulses and therefore, set apart the clock down to 1Hz. And this 1Hz signal is fed into the SECOND...If you want to gravel a full essay, aim it on our website: Orderessay

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